As the use of digital data increases, the demand for faster, smaller, and more efficient memory structures increases. One type of memory structure that has recently been developed is a single memristor crossbar memory array. A crossbar memory array includes a first set of conductive lines which perpendicularly intersect a second set of conductive lines. A programmable memory cell configured to store digital data is placed at each intersection of the lines.
One type of device which can be used as a memory cell is a resistive switch such as a memristor. Using memristive devices as resistive devices on a crossbar array brings up several design constraints. For example, when applying read/write voltages to a selected memory cell, care must be taken to prevent excessive leakage current from passing through unselected memory cells. Additionally, during read operations, leakage current through unselected cells can affect the measurements taken by a sense amplifier. Thus, the number of memory cells along a particular wire which are in a low resistive state may have to be limited.
One way to reduce the leakage current is to use two memristive devices in series at each intersection of lines in a memory array. These two memristive devices can be placed in a complementary manner. If two memristors are connected in a complementary manner, then one memristor is in a high resistive (OFF) state while the other memristor is in a low resistive (ON) state. The combined resistance will always be in a high resistive state. This reduces the leakage current within the memory array. If the memristor which is initially in an OFF state is switched to an ON state, then the other memristor will be switched from an ON state to an OFF state. One of the two memristive devices placed in this complementary manner can be used to represent digital data. For example, an ON state may represent a digital ‘1’ and an OFF state may represent a digital ‘0’.
When memristive devices are placed in a complementary manner as described above, they can exhibit a property that results in a destructive read. When reading the state of a memory cell with a destructive read, the state of the memory cell is lost during the read process. The original state must then be written back to the memory cell after the read operation is completed. This takes additional time and power, thus reducing the speed and power efficiency at which the memory array is able to operate.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.